In recent years, a memory device has been proposed in which a material having two resistance states is utilized. A three-dimensional cross-point structure has been proposed as a structure for integrating memory cells in such a memory device in which the memory cells are disposed at the crossing points between word lines and bit lines. The memory device having the three-dimensional cross-point structure is advantageous for higher integration; but the stability of the operations is a problem.
FIG. 1 is a perspective view showing a memory device according to the comparative example.
FIG. 2A and FIG. 2B are circuit diagrams showing the memory device according to the comparative example.
As shown in FIG. 1, the configuration of the memory device 101 according to the comparative example is a so-called three-dimensional cross-point structure. In the memory device 101, the bit line interconnect layers BLL and the word line interconnect layers WLL are stacked alternately; and the variable resistance members RC are connected between the bit lines BL and the word lines WL.
In the memory device 101 according to the modification as shown in FIG. 2A and FIG. 2B, the bit line interconnect layer BLL or the word line interconnect layer WLL is shared between the mutually-adjacent memory cell layers ML. Therefore, when applying the set potential Vset to the selected bit line connected to the selected cell MCs, the set potential Vset is applied also to one of the memory cell layers ML positioned adjacently on two sides of the memory cell layer ML to which the selected cell MCs belongs. Also, when applying the reference potential Vs to the selected word line WLs connected to the selected cell MCs, the reference potential Vs is applied also to the other of the memory cell layers ML positioned adjacently on the two sides. At this time, the interaction with the selected cell MCs is large because the memory cell layer ML to which the set potential Vset is applied and the memory cell layer ML to which the reference potential Vs is applied are disposed adjacent to the memory cell layer ML to which the selected cell MCs belongs. Therefore, the likelihood that misoperations may occur is high.
To relax the voltage between the interconnects in the adjacent memory cell layers ML to which the set potential Vset or the reference potential Vs is applied, it also may be considered to apply an appropriate potential to the other interconnects. However, in the memory device 101, because the memory cell layers ML are arranged to be continuous while sharing the bit line interconnect layer BLL or the word line interconnect layer WLL, when applying a potential to one memory cell layer ML, it is necessary to apply potentials also to the memory cell layers ML adjacent to the one memory cell layer ML to reduce the effects; and the driving is exceedingly complex.